1. Field of the Invention
The present invention relates to a semiconductor storage device and its control method.
2. Description of Related Art
In recent years, as mobile digital terminals have become more sophisticated, it has been desired to process a huge amount of digital data at very high speed. To achieve such high-speed processing, it is necessary to use a memory capable of temporarily storing data at a high speed as well as a high-performance MPU (Micro Processing Unit) processing device.
However, the improvement in operation speed of memories (for example, DRAMs, which are commonly used as larger-capacity RAMs (Random Access Memories)) has been significantly slower in comparison to the improvement in operation speed of MPUs, and the improvement in operation speed of memories has become a critical problem to be solved in the speeding-up of digital data processing.
Therefore, high-speed data transfer techniques like the one called “DDR (Double Data Rate)” have been used in the past. However, the novel feature of such transfer techniques is merely that only the data transfer in which data is synchronized with a clock and transmitted through a dedicated data transfer pin is made faster, and the fundamental configuration as a memory has not changed significantly from the conventional ones.
In the conventional memories, data input and output are both carried out only through data input and output terminals.
Further, Japanese Unexamined Patent Application Publication No. S60-236185 discloses a semiconductor memory capable of changing the number of output bits. This memory includes output bit change means that enables a certain terminal to have variable functions in a programmable manner so that the terminal is used as an address input terminal or an output terminal, or an input/output terminal.
Note that, in general, data stored in a memory is frequently rewritten. That is, once data corresponding to a certain address is read and processed by an MPU, the MPU often writes new data at the same address to execute a subsequent process.
However, in the memory disclosed in Japanese Unexamined Patent Application Publication No. S60-236185, it seems possible to increase the data transfer amount by expanding the output bit wide. However, for the operation in which reading and writing are performed in succession, it is necessary to perform the successive writing after the successive reading is completed. That is, in the memory disclosed in Japanese Unexamined Patent Application Publication No. S60-236185, when reading and writing of data corresponding to the same address are performed, the operation speed is not increased in comparison to the conventional products.
In contrast to this, Japanese Unexamined Patent Application Publication No. H7-312080 discloses a memory that is equipped with separate data input terminals and data output terminals so that data writing and data reading can be performed in parallel.